High-K dielectric with Metal Gate electrodes (HKMG) has been proven to be one of the most critical innovations that allows further gate thickness scaling, which in turn enables the active channel length scaling and the overall performance boost in advanced CMOS technology. Furthermore, the Replacement Gate (RMG) integration flow for HKMG provides additional advantage in terms of thermal budget control. However, in a typical HKMG RMG flow, gate dielectric, including the high-K gate can become exposed after the metal gate CMP process. This can provides an oxygen ingress path and lead to oxide regrowth at gate channel interface during the subsequent Middle of Line (MOL) dielectric deposition and Back End of the Line (BEOL) processing. The oxide regrowth increases the effective dielectric thickness and shifts the transistor threshold voltage, both of which can cause severe device degradation in terms of performance and variability. Thus, the oxygen ingress and regrowth at high-K gate dielectric to semiconductor channel interface should be avoided.
In the prior art, after the metal-gate CMP is completed, the next layer, usually silicon nitride, is typically deposited at temperatures high enough (>500° C.) that the exposed high-K gate dielectric material can absorb any oxygen present during the deposition process, and transport the oxygen towards the gate dielectric to channel interface region, where the oxygen causes an unwanted regrowth. The deposition temperature is important because higher temperatures increase the absorption and diffusion of oxygen into the high-K gate dielectric, towards the gate dielectric to channel interface.
FIGS. 1 to 8 illustrate prior art for High-K Metal Gate (HKMG) Field Effect Transistor (FET), using the Replacement Metal Gate (RMG) integration scheme, also known as Gate-Last integration.
FIG. 1 shows starting with a semiconductor substrate which can be formed of any semiconductor such as silicon, germanium, silicon-germanium or other compound semiconductors, the subsequent structures are built. Shown, is the formation of a sacrificial gate, which is formed by conventional deposition or growth of a sacrificial gate dielectric, such as SiO2 or other suitable dielectric, and deposition of a poly-crystalline or amorphous semiconductor, such as silicon or germanium or any compound semiconductor, followed by standard gate lithography and etching to form gate structures. Also shown is a spacer formed by conventional deposition of silicon nitride or other suitable spacer dielectric and standard anisotropic Reactive Ion Etch (RIE) techniques.
FIG. 2 shows the formation of standard source/drain regions formed by ion implantation of dopants, or embedded source/drain formed by etching a trenched, then refilled by epitaxial deposition of doped semiconductor, such as silicon, silicon-germanium, silicon carbon, or other materials, or a combination of ion implantation and epitaxial source/drain formation. As mentioned previously, the source/drain region can be either n-type for NFET or p-type for PFET devices, which can be achieved by utilizing conventional lithography and patterning techniques.
FIG. 3 shows the deposition of an interlayer dielectric (ILD) such as silicon oxide or other suitable dielectric, which is then planarized by conventional Chemical Mechanical Polishing (CMP). The sacrificial gate is removed by a selective wet or plasma etch that removes the sacrificial gate material but not the ILD, nor the spacer material. The sacrificial gate dielectric can also be removed at the step if desired, or it can be retained and incorporated into the final structure. For the purposes of the description, the sacrificial gate dielectric is removed.
FIG. 4 shows the deposition of a gate dielectric stack which can have a single or multiple layers such as an interface oxide or oxynitride layer and high-K dielectric layers such as hafnium oxide, hafnium silicate or other high-K materials. Also shown is the deposition of a workfunction metal material such as TiN on top of the gate dielectric stack. The purpose of the workfunction metal layer is to set the appropriate workfunction to achieve the desired transistor threshold voltage (Vth). The workfunction layer can be a single layer or multiple layers. It should be understood that NFET and PFET transistors may require different workfunction metal layers, which can be achieved by conventional lithography and patterning techniques to place n-type workfunction metal layers in NFET transistor regions and p-type workfunction metal layers in PFET transistor regions.
FIG. 5 shows an additional metal gate deposition on top of the workfunction metal to completely fill the gate region. The metal gate material can be W, Al or other suitable metal which provides a low resistance gate contact or stacks of different metals. The metal gate material can be different between NFET and PFET transistors.
FIG. 6 shows the structure after a conventional metal gate CMP process has been performed to planarize the surface to the top of the gate. The CMP process removes the metal gate, workfunction metal and high-K gate dielectric stacks from the top surface of the wafer, leaving those materials only within the gate. Note also, that because of the CMP process, the top periphery of the high-K dielectric is exposed to the ambient environment during subsequent process steps. In particular, if that ambient environment in subsequent process steps contains any oxygen and the temperature is high enough (>500° C.), the exposed top periphery of the high-K dielectric stack will absorb that oxygen and transport it by diffusion to the gate dielectric to semiconductor channel interface, which causes several problems as will be described in a subsequent section.
FIG. 7 shows the deposition of a middle of line (MOL) dielectric such as silicon nitride or oxide or other suitable dielectric material, which is typically deposited by chemical vapor deposition (CVD) or other conventional techniques at a temperature exceeding 500° C. Because the ambient of the deposition process typically contains some oxygen, the oxygen will be absorbed by the exposed top periphery of the high-K dielectric and transported by diffusion to the gate dielectric to semiconductor channel interface, which causes several problems as will be described in a subsequent section.
FIG. 8 shows in additional detail the structure in FIG. 7, and the issues created by the standard replacement metal gate processing in prior art. As described previously, after the metal gate CMP process to planarize and remove the metal gate, workfunction metal and high-K gate dielectric materials from the top surface of the wafer, the top periphery of the high-K gate dielectric is exposed to ambient of the next process step. The next process step is a conventional MOL dielectric deposition of either silicon nitride or oxide or other suitable dielectric material which is performed at a temperature of 500° C. or more. Because the ambient of these deposition processes typically contains some residual oxygen, the oxygen will be absorbed by the exposed top periphery of the high-K dielectric and transported by diffusion to the gate dielectric to semiconductor channel interface. When oxygen diffuses to the gate dielectric to semiconductor channel interface, several problems can occur. First, the oxygen grows additional unwanted oxide at the critical gate dielectric to semiconductor channel interface, which thickens the effective oxide thickness (EOT) of the gate dielectric stack, which reduces transistor performance. Second, the oxygen shifts transistor Vth away from the desired Vth set point. Third, because the oxygen diffusion and ingress into the gate dielectric to semiconductor channel interface is not well controlled and varies significantly across wafer and from wafer to wafer during processing, both the EOT thickness increase and Vth shifts are highly variable, which severely degrades the overall semiconductor chip performance and manufacturability.
Accordingly, there is a need for a structure and method to minimize the oxygen ingress and diffusion into the gate dielectric to semiconductor channel interface in RMG FET structure and process.